DRAM Caching
نویسندگان
چکیده
This paper presents methods to reduce memory latency in the main memory subsystem below the board-level cache. We consider conventional page-mode DRAMs and cached DRAMs. Evaluation is performed via trace-driven simulation of a suite of nine benchmarks. In the case of page-mode DRAMs we show that it can be detrimental to use page-mode naively. We propose two enhancements that reduce overall memory latency in this case: one is the remapping of address bits and the other is selective usage of page-mode under the control of the memory controller. In the case of cached DRAM we quantify the improvements that can be attained by introducing some SRAM cache on the DRAM chip. We evaluate various design alternatives for the line size and associativity of the SRAM cache.
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